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T0088-S

A Field Programmable Gate Array (FPGA) -based, Radiation Tolerant, Reconfigurable Computer System with Real Time Fault Detection, Avoidance, and Repair

PI: Brock LaMeres, Todd Kaiser (Co-I), Montana State University - Bozeman

The goal of this project is to mature the technology readiness level of a radiation tolerant, reconfigurable computer system that has been developed at Montana State University (MSU). The improved radiation tolerance delivered by our approach makes reconfigurable computing using commercial FPGA fabrics a reality.

Next on the Pad: RadSat - A Radiation Tolerant Computer System

Feb 2018: ISS Database entry on 3U RadSat-g
Nov 2017: Research Overview video
Sep 2017: MSU team receives NASA grant to launch satellite from space station
Jan 2017: Two MSU projects receive NASA grants to fund student flight research opportunities
Jan 2017: MSU researchers test computer technology on International Space Station
Dec 2016: Video of installation onboard the ISS
Dec 2016: ISS Database entry on Radiation Tolerant Computer Mission on the ISS (RTcMISS)
Sep 2016: 2015 Annual Report story on Radiation Tolerant Computer System

Technology Areas (?)
  • TA04 Robotics, Tele-Robotics and Autonomous Systems
  • TA11 Modeling, Simulation, Information Technology and Processing
Problem Statement

The goal is to mature the technology readiness level of the radiation tolerant, reconfigurable computer system by testing in a relevant end-to-end environment on a suborbital vehicle. To meet this goal, we need to accomplish the following objectives: (1) Implement the computer system in a form factor to meet the payload requirements of the selected suborbital vehicle; (2) Develop the power system for the payload following the requirements of the selected suborbital vehicle; and (3) Perform pre-integration testing of the system following the requirements of the selected suborbital vehicle.

Technology Maturation

Flying the system on the UP Aerospace SL-9 vehicle exceeded the original project scope. The new implementation of the computer system (in a 1U form-factor to support subsequent flight demonstrations) was able to operate for 6.5 hours on batteries and log the system counter status, the computation FPGA’s die temperature, and the G-force switch status to an SD-card while operating in a harsh temperature, vibration, acceleration, and micro-gravity environment provided by the SL-9 vehicle.

Future Customers

The opportunity to demonstrate the computer system on a suborbital vehicle through the Flight Opportunities Program was instrumental in maturing the technology to TRL-6. This allowed the hardware to move from a laboratory prototype to a fully functional flight unit. The computer system hardware is moving steadily toward a robust enough platform for subsequent flight demonstrations with minimal investment to achieve the next levels of TRL.

Technology Details

  • Selection Date
    NRA-1-APP-A (Jul 2012)
  • Program Status
    Completed
  • Current TRL (?)
    TRL 4
    Successful FOP Flights
  • 2 sRLV

Development Team

Web Accessibility and Privacy Notices Curator: Alexander van Dijk Responsible NASA Official: Stephan Ord Last Update: November 16, 2018