An FPGA-based, Radiation Tolerant, Reconfigurable Computer System with Real Time Fault Detection, Avoidance, and Repair

PI: Brock LaMeres, Montana State University

The goal of this project is to mature the technology readiness level of a radiation tolerant, reconfigurable computer system that has been developed at Montana State University (MSU). The improved radiation tolerance delivered by our approach makes reconfigurable computing using commercial FPGA fabrics a reality. This in turn promises to deliver increased computing performance at lower power and cost compared to existing radiation tolerant technologies. Our research team has developed a novel computer system that uses a variety of fault mitigation techniques to provide increased reliability in harsh radiation environments. This technology has sofar been tested at the Texas A&M Radiation Effects Facility and on a high altitude balloon platform up to 100,000 feet.

Paper at 2015 Smallsat Conference

T0088-S was selected for a NASA Smallsat Technology Partnership

Technology Areas (?)
  • TA11 Modeling, Simulation, Information Technology and Processing
Problem Statement

The goal is to mature the technology readiness level of the radiation tolerant, reconfigurable computer system by testing in a relevant end-to-end environment on a suborbital vehicle. To meet this goal, we need to accomplish the following objectives: (1) Implement the computer system in a form factor to meet the payload requirements of the selected suborbital vehicle; (2) Develop the power system for the payload following the requirements of the selected suborbital vehicle; and (3) Perform pre-integration testing of the system following the requirements of the selected suborbital vehicle.

Technology Maturation

With respect to the original project objectives, flying the system on the UP Aerospace SL-9 vehicle exceeded the original project scope. The new implementation of the computer system (in a 1U form-factor to support subsequent flight demonstrations) was able to operate for 6.5 hours on batteries and log the system counter status, the computation FPGA’s die temperature, and the G-force switch status to an SD-card while operating in a harsh temperature, vibration, acceleration, and micro-gravity environment provided by the SL-9 vehicle. This flight was a major milestone in maturing the technology for a demonstration in an operational environment.

The opportunity to demonstrate the computer system on a suborbital vehicle through the Flight Opportunities Program was instrumental in maturing the technology to TRL-6. This allowed the hardware to move from a laboratory prototype to a fully functional flight unit. The computer system hardware is moving steadily toward a robust enough platform for subsequent flight demonstrations with minimal investment to achieve the next levels of TRL. Another aspect of this opportunity was the crucial training of university faculty and students on conducting a rigorous aerospace flight campaign.

Future Customers


Technology Details

  • Selection Date
    NRA1 (July 2012)
  • Program Status
  • Current TRL (?)
    TRL 4
    Successful FOP Flights
  • 2 sRLV

Development Team

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